1. Field of the Invention
The present invention relates to a method of fabricating a fringe field switching (FFS)-liquid crystal display (LCD) device, and particularly, to a method of fabricating an FFS-LCD device capable of implementing a high resolution and a wide viewing angle.
2. Related Art of the Invention
As concerns about information displays and demands for portable information media increase, research and commercialization of flat panel displays (FPD) replacing the conventional display apparatus, Cathode Ray Tubes (CRT) are actively ongoing. One of these flat panel displays, a Liquid Crystal Display (LCD) device serves to display an image by using optical anisotropy of a liquid crystal (LC). Owing to an excellent resolution, color reproduction characteristic, and picture quality, the LCD device is being actively applied to a notebook, a desk top monitor, etc.
The LCD device is comprised of a color filter substrate, an array substrate, and an LC layer interposed between the color filter substrate and the array substrate.
Hereinafter, a structure of the related art LCD device will be explained in more detail with reference to FIG. 1.
FIG. 1 is a disassembled perspective view schematically showing a structure of the related art LCD.
As shown in FIG. 1, the LCD device comprises a color filter substrate 5, an array substrate 10, and an LC layer 30 interposed between the color filter substrate 5 and the array substrate 10.
The color filter substrate 5 consists of a color filter (C) composed of a plurality of sub color filters 7 for implementing red, green and blue (RGB) colors, a black matrix 6 for dividing the sub color filters 7 from each other and shielding light passing through the LC layer 30, and a transparent common electrode 8 for applying a voltage to the LC layer 30.
The array substrate 10 consists of a plurality of gate lines 16 and data lines 17 arranged in horizontal and vertical directions to define a plurality of pixel regions (P), Thin Film Transistors (TFT), switching devices formed at each intersection between the gate lines 16 and the data lines 17, and pixel electrodes 18 formed in the pixel regions (P).
The color filter substrate 5 and the array substrate 10 facing each other are bonded to each other by a sealant (not shown) formed on an outer periphery of an image display region, thereby constituting an LC panel. The color filter substrate 5 and the array substrate 10 are bonded to each other by bonding keys (not shown) formed at the color filter substrate 5 or the array substrate 10.
The LCD device is generally driven by a twisted nematic (TN) method for driving nematic LC molecules in a direction perpendicular to a substrate. However, the TN method has a disadvantage that an LCD device has a narrow viewing angle of 90°. This results from refractive anisotropy of LC molecules. More concretely, LC molecules aligned in a direction parallel to a substrate are re-aligned in a direction perpendicular to the substrate when a voltage is applied to a panel.
In order to solve the disadvantage, has been proposed an In Plane Switching (IPS)-LCD device capable of widening a viewing angle to an angle more than 170° by driving LC molecules in a direction parallel to a substrate. This will be explained in more details.
FIGS. 2 and 3 are sectional views showing part of an array substrate of an IPS-LCD device, which schematically shows part of an array substrate of a Fringe Field Switching (FFS)-LCD device. The FFS-LCD device displays an image by driving LC molecules disposed on a pixel region and a common electrode, by allowing a fringe field formed between a pixel electrode and a common electrode to penetrate through a slit.
In the FFS-LCD device, in a state that LC molecules are horizontally aligned, a common electrode is formed at a lower part and a pixel electrode is formed at an upper part. This may generate an electric field in horizontal and vertical directions, thereby allowing LC molecules to be twisted and tilted.
FIG. 2 shows that an array substrate has been fabricated by performing a photolithography process (hereinafter, will be referred to as a mask process) six times, and FIG. 3 shows that an array substrate has been fabricated by performing a mask process five times.
Referring to FIGS. 2 and 3, in the related art FFS-LCD device, gate lines (not shown) and data lines (not shown) are horizontally and vertically arranged on the transparent array substrate 10, thereby defining pixel regions. A switching device, a thin film transistor (TFT) is formed at each intersection between the gate lines and the data lines.
The TFT consists of a gate electrode 21 connected to the gate line, a source electrode 22 connected to the data line, and a drain electrode 23 connected to the pixel electrode 18. And, the TFT includes a gate insulation film 15a for insulating the gate electrode 21 from the source electrode 22 and the drain electrode 23, and an active layer 24 for forming a conductive channel between the source electrode 22 and the drain electrode 23 by a gate voltage supplied to the gate electrode 21.
Source and drain regions of the active layer 24 form ohmic contacts together with the source electrode 22 and the drain electrode 23, through an ohmic contact layer 25n. 
The common electrode 8 and the pixel electrode 18 are formed in the pixel region. The common electrode 8 includes a plurality of slits (8s) therein so as to generate a fringe field together with the pixel electrode 18 of a box shape.
The pixel electrode 18 of FIG. 2 is electrically connected to the drain electrode 23 via a contact hole of a first passivation film 15b, and the pixel electrode 18 of FIG. 3 is directly electrically connected to the drain electrode 23 without a contact hole.
Reference numeral 15c of FIG. 2 denotes a second passivation film.
The array substrate is bonded to a color filter substrate by a sealant formed at an outer periphery of an image display region, in a state that a cell gap is constantly maintained between the array substrate and the color filter substrate by a column spacer. The color filter substrate is provided with the TFTs, black matrixes for preventing light leakage to the gate lines and the data lines, a color filter for implementing red, green and blue (RGB) colors, and an overcoat layer.
The FFS-LCD device has an advantage that a viewing angle is wide. Furthermore, the FFS-LCD device is capable of enhancing an aperture ratio by reducing regions of black matrixes in a case that the common electrode is formed over the data lines.
Generally, the array substrate including TFTs is fabricated through a plurality of mask processes. For enhanced productivity, it is required to reduce the number of mask processes. However, the FFS-LCD device of FIG. 3 fabricated through mask processes having a frequency reduced by a single process may have an inferiority that Indium Tin Oxide (ITO) of a pixel electrode connected to a drain electrode is eroded.
FIGS. 4A to 4E are sectional views sequentially showing processes of fabricating the array substrate of FIG. 3.
As shown in FIG. 4A, a gate electrode 21 formed of a conductive metallic material, and a gate line (not shown) are formed on an array substrate through a photolithography process (first mask process).
Then, as shown in FIG. 4B, on the array substrate 10 having thereon the gate electrode 21 and the gate line, sequentially deposited are a gate insulation film 15a, an amorphous silicon thin film, an n+ amorphous silicon thin film and a conductive metallic material.
Then, the amorphous silicon thin film, the n+ amorphous silicon thin film, and the conductive metallic material are selectively patterned through a photolithography process (second mask process), thereby forming an active layer 24 formed of the amorphous silicon thin film in a state that the gate insulation film 15a has been disposed on the gate electrode 21. And, the source electrode 22 and the drain electrode 23 formed of the conductive material are formed on the active layer 24. Data lines (not shown) which define pixel regions together with the gate lines are formed through the second mask process.
Between the active layer 24 and the source and drain electrodes 22 and 23, formed is an ohmic-contact layer 25n for ohmic-contacting the active layer 24 and the source and drain electrodes 22 and 23 with each other.
As shown in FIG. 4C, a transparent conductive material is deposited on an entire surface of the array substrate 10, and then is selectively patterned through a photolithography process (third mask process). As a result, formed is a pixel electrode 18 electrically connected to the drain electrode 23.
As shown in FIG. 4D, a passivation film 15b is deposited on an entire surface of the array substrate 10 where the source electrode 22, the drain electrode 23 and the data lines have been formed. Then, part of the passivation film 15b is removed through a photolithography process (fourth mask process), thereby forming a contact hole (not shown).
Finally, as shown in FIG. 4E, a transparent conductive material is deposited on an entire surface of the array substrate 10, and then is selectively patterned through a photolithography process (fifth mask process). As a result, implemented is a common electrode 8 formed of the transparent conductive material. The common electrode 8 includes a plurality of slits (8s) therein so as to generate a fringe field together with the pixel electrode 18 disposed therebelow.
In the FFS-LCD device, the number of mask processes may be reduced by a single process since the pixel electrode is directly formed on the drain electrode. However, ITO of the pixel electrode connected to the drain electrode may be partially eroded due to problems occurring during the process. This will be explained in more details with reference to the drawings.
FIGS. 5A to 5I are sectional views showing second and third mask processes of FIGS. 4B and 4C.
As shown in FIG. 5A, on an entire surface of the array substrate 10 where the gate electrode 21 and the gate lines have been formed, sequentially deposited are a gate insulation film 15a, an amorphous silicon thin film 20, an n+ amorphous silicon thin film 25 and a conductive metallic material 30.
On the conductive metallic material 30, disposed is a photosensitive film formed of a photosensitive material such as a photoresist. Then, the photosensitive film is selectively irradiated with light through a mask.
Once the exposed photosensitive film is developed, first to third photosensitive film patterns 60a˜60c of a predetermined thickness remain in a shielding region and a second transmission region where light has been completely or partially shielded. And, the conductive metallic material 30 is exposed to a first transmission region where light has been completely transmitted.
As shown in FIG. 5B, part of the conductive metallic material is removed, through a wet etching, by using the first to third photosensitive film patterns 60a˜60c as a mask. As a result, a conductive film pattern 30′ formed of the conductive metallic material is disposed on the array substrate 10.
As shown in FIG. 5C, the amorphous silicon thin film and the n+ amorphous silicon thin film are partially removed, through a dry etching, by using the first to third photosensitive film patterns 60a˜60c as a mask. As a result, below the conductive film pattern 30′, disposed are an active layer 24 and an n+ amorphous silicon thin film pattern 25′ formed of the amorphous silicon thin film and the n+ amorphous silicon thin film, respectively.
Then, an ashing process is performed to partially remove thicknesses of the first to third photosensitive film patterns 60a˜60c. As a result, as shown in FIG. 5D, a third photosensitive film pattern of the second transmission region is completely removed.
The first photosensitive film pattern and the second photosensitive film pattern have a thicknesses removed by a thickness of the third photosensitive film pattern, thereby remaining only in the shielding region as a fourth photosensitive film pattern 60a′ and a fifth photosensitive film pattern 60b′, respectively.
As shown in FIG. 5E, the conductive film pattern is partially removed, through a wet etching, by using the fourth photosensitive film pattern 60a′ and the fifth photosensitive film pattern 60b′ as a mask. As a result, on the n+ amorphous silicon thin film pattern 25′, disposed is a source electrode 22 and a drain electrode 23 formed of the conductive metallic material.
As shown in FIG. 5F, the n+ amorphous silicon thin film pattern is partially removed, through a dry etching, by using the fourth photosensitive film pattern 60a′ and the fifth photosensitive film pattern 60b′ as a mask (hereinafter, will be referred to as a back channel-etch). As a result, implemented is an ohmic-contact layer 25n formed of the n+ amorphous silicon thin film.
Generally, the dry etching is performed by using a gas mixture of SF6, Cl2, He, etc., and the SF6 and the Cl2 react with copper (Cu) of the drain electrode 23, thereby forming a copper compound such as CuF2 and CuCl2.
Then, as shown in FIG. 5G, the fourth photosensitive film pattern 60a′ and the fifth photosensitive film pattern 60b′ are removed through a dry strip.
Generally, the dry strip is performed by using a gas mixture of SF6, O2, etc., and the SF6 reacts with copper (Cu) of the drain electrode 23, thereby forming a copper compound such as CuF2.
As shown in FIG. 5H, a transparent conductive metallic material 50 such as ITO is deposited on an entire surface of the array substrate 10, and then a photosensitive film pattern 65 is formed through a mask process.
As shown in FIG. 5I, part of the ITO is removed, through a wet etching, by using the photosensitive film pattern 65 as a mask. As a result, implemented is a pixel electrode formed of the ITO.
The ITO deposited on the drain electrode 23 is eroded when the pixel electrode 18 is patterned, since a bonding force with the drain electrode 23 has lowered due to the copper compound such as CuF2 and CuCl2 formed on the drain electrode 23 through the aforementioned back channel-etch and the dry strip.
The copper is used to form a data wire, e.g., a source electrode, a drain electrode and a data line, since it effectively serves as a low resistance wire. However, controlling the process is difficult since the copper is rapidly oxidized due to an excellent surface reactivity, or since the copper has a new coupling structure by reacting with another gas. Especially, in a case that the wire is formed of copper, a resistance may increase according to a surface state, or connection inferiority with ITO may occur.